The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++, System Verilog and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.
The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog's Universal Verification Methodology (UVM) is preferred.
Basic understanding of Digital Design fundamentals
Knowledge of all phases of ASIC design and test methodology
Expertise in Verilog / VHDL and System Verilog
Experience in developing Verification Environment
Experience in Unit Level and Top Level Verification
Experience in developing BFM's and VIP's
Proficiency in Test plan development
Proficiency with industry standard simulators
Scripting Skills - Shell, TCL, etc
Good Communication Skills
Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
Knowledge of System Verilog
Knowledge of UVM
Test Planning & Verification
Knowledge of safety standards desirable
Working Knowledge of various tools
Synopsys - VCS
Proficiency in ARM Architecture
Gate Level Simulation experience
Low Power Simulation experience
Dynamic CDC experience
EXPERIENCE AND EDUCATION:
A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
Minimum of 3 years' experience with standard cell ASIC and / FPGA design.
Candidate should be familiar with RTL, gate level design and verification using VHDL and/or Verilog hardware description languages.
Demonstrated ability designing independently for medium/high complexity problems.
Strong oral and written communication skills in English and ability to present technical information.
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